Semiconductor dies or chips are frequently embedded in a molding composition to produce packages. In modern uses, small packages, commonly known as Chip Scale Packages, are frequently preferred. Chip Scale Packages, or CSPs, based on the IPC/JEDEC J-STD-012 definition, are single-die, direct surface mountable packages with an area no more than 20% greater than the original die area. The IPC/JEDEC definition does not specify a particular design or construction of a chip scale package, so any package that meets the surface mountability and dimensional requirements of the definition may be viewed as a CSP.
The advantages offered by chip scale packages include small size, reduced weight, and improvement in electrical performance. The small size of a CSP makes it useful in portable devices, such as cell phones, laptops, palmtops, and digital cameras.
Wafer-level Chip Scale Packages (WL-CSPs) may be made by extending wafer fabrication processes to include device interconnection and device protection processes. Redistribution Layer and Bump technology, the most widely-used WL-CSP technology, extends the conventional fabrication process with an additional step that deposits a thin-film metal rerouting and interconnection system on the surface of the wafer by photolithography and thin film deposition techniques. This metal rerouting and interconnection system redistributes the bonding pads from the periphery of the upper surface of each chip to an array of metal bonding pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these evenly deployed bonding pads. This redistribution technique improves chip reliability by allowing the use of larger and more robust balls for interconnection between the bonding pads and the leadframe.
However, the WL-CSP technology described has inherent limitations because it arranges solder balls directly on a surface of the die and, since the solder balls must have greater than a certain minimum spacing to avoid contact between adjacent solder balls, the larger the number of solder balls that are required means the larger the required chip area. This requirement for a large area on which to arrange the solder bumps may still persist even after deposition of a redistribution layer with an array of metal bonding pads that are evenly deployed over the chip's surface.